DRAMs (dynamic random access memory) serve for storing and reading items of information. They have memory cells arranged in matrix form in a memory cell array and each comprising a selection transistor and a storage capacitor. In this case, an item of digital information, i.e., a “0” or a “1,” is defined via a charge on the storage capacitor. In order to change the charge state of a memory cell, the memory cells arranged in matrix form are connected to bit lines via a drain of the selection transistor, gates of the selection transistors being able to be driven via word lines running perpendicular with respect to the bit lines. A specific memory cell can thus be driven individually via the bit line and word line of the selection transistor. By switching on the gate of the selection transistor, charge can either be stored on the storage capacitor via the bit line or else be read out from the storage capacitor via the bit line. A sense amplifier is used for reading purposes, two bit lines BL and /BL being connected to the sense amplifier. Before a read operation, the two bit lines BL and /BL are precharged to a voltage VBLEQ, the voltage VBLEQ, as is known, corresponding to half of a bit line high voltage level value VBLH, VBLH representing the voltage of a bit line for writing a “1” to a memory cell. If the two bit lines BL and /BL are at the voltage VBLEQ, then the gate of the selection transistor of the memory cell to be read is opened, and the potential of that one of the two bit lines BL and /BL to which the memory cell to be read is connected changes. The potential change on the corresponding bit line relative to the potential VBLEQ on the other bit line is amplified by the sense amplifier and represents the read signal. In this case, the read signal depends on the voltage difference between a high (“1”) and low (“0”) level of the storage capacitor, the capacitance of the storage capacitor and also a parasitic capacitance of the bit line including the input capacitance of the sense amplifier.
The probability of correctly identifying a “0” and “1” memory state of a memory cell depends for example on leakage currents or the bias voltage of the sense amplifier. Shifting the VBLEQ level on the bit lines to values that are different from VBLH/2 during a precharge operation would on average increase the probability of correctly detecting the memory state of the memory cell and thus lead to an increase in the reading accuracy. A corresponding change in the output voltage of a VBLEQ voltage source to which the bit lines BL and /BL are connected in the precharge state does not achieve the desired success, however, as is explained below. During the precharging of the bit lines after a memory cell access, the bit lines BL and /BL connected to the sense amplifier are short-circuited with one another. Since one of these bit lines is at 0 V, i.e., low level, and the other is at VBLH, i.e., high level, and both bit lines have the same capacitance, a potential value of VBLH/2 is established as a result of capacitive charge reversal on the two bit lines. Since the connection of the bit lines to VBLEQ voltage sources usually leads via a very large resistance in order, for example, to limit leakage currents in the case of short circuits between word and bit lines, the voltage established as a result of the short-circuiting of the two bit lines is dominant over the output voltage provided by the VBLEQ voltage source. This prevents the precharge voltage of the bit lines from being changed to values that are different from VBLH/2 by simply changing the output voltage of a VBLEQ voltage source.
When the gate of the selection transistor is opened during a read operation and the storage node of a DRAM cell is thus connected to one of the bit lines, the effective capacitance of the bit line increases. In the case of the cross-coupled differential sense amplifiers that are usually used in DRAM semiconductor memory devices, this results in impairment of the reading accuracy on account of the capacitive disequilibrium. Such impairments of the reading accuracy adversely affect the yield of the DRAMs.